Using SPI with shift registers - Revision history

Psmay: /* 74HC165 and similar */

2018-03-02T14:24:47Z

74HC165 and similar

Psmay: /* '165 and '595 in same transaction */

2018-02-26T21:01:32Z

'165 and '595 in same transaction

Psmay at 20:57, 26 February 2018

2018-02-26T20:57:54Z

Psmay: /* 74HC595 and similar */

2018-02-24T21:38:36Z

74HC595 and similar

Psmay at 16:18, 23 February 2018

2018-02-23T16:18:30Z

Psmay at 13:57, 23 February 2018

2018-02-23T13:57:03Z

Psmay: Created page with "==74HC165 and similar== // 74HC165 connection via SPI #include // UNO SPI '165 // 9* n/a storage clock (ST_CP, /PL, DIP #1) /..."

2018-02-23T03:18:23Z

Created page with "==74HC165 and similar== <syntaxhighlight lang=cpp> // 74HC165 connection via SPI #include <SPI.h> // UNO SPI '165 // 9* n/a storage clock (ST_CP, /PL, DIP #1) /..."

New page

==74HC165 and similar==

<syntaxhighlight lang=cpp>

// 74HC165 connection via SPI

#include <SPI.h>

// UNO SPI '165
// 9* n/a storage clock (ST_CP, /PL, DIP #1)
// 10* NSS shift clock inhibit (CLK INH, /CE, DIP #15)
// 11 MOSI n/c
// 12 MISO serial data output (Q7, DIP #9)
// 13 SCK shift clock (SH_CP, CP, DIP #2)

// Note that the storage clock and the NSS can be anywhere. Rumor says that
// on the UNO pin 10 must be OUTPUT for the SPI master to work, but it need
// not be the actual select pin.

const uint8_t IM_STO = 9;
const uint8_t IM_NSS = 10;

const unsigned long IM_MAX_SPEED = 4000000; // A guess; could probably do way faster
const uint8_t IM_BIT_ORDER = MSBFIRST;
const uint8_t IM_SPI_MODE = SPI_MODE0;

void setup() {
pinMode(IM_STO, OUTPUT);
digitalWrite(IM_STO, true);
pinMode(IM_NSS, OUTPUT);
digitalWrite(IM_NSS, true);

Serial.begin(115200);
Serial.println("start");

SPI.begin();
}

void sendStorePulse() {
digitalWrite(IM_STO, false);
delayMicroseconds(5);
digitalWrite(IM_STO, true);
delayMicroseconds(5);
}

uint8_t loadBySpi() {
// Select device and begin transaction
digitalWrite(IM_NSS, false);
SPI.beginTransaction(SPISettings(IM_MAX_SPEED, IM_BIT_ORDER, IM_SPI_MODE));

// Perform transfer
uint8_t receivedData = SPI.transfer(0x00);

// End transaction and deselect device
SPI.endTransaction();
digitalWrite(IM_NSS, true);

return receivedData;
}

void loop() {
sendStorePulse();
uint8_t reading = loadBySpi();

Serial.print("SPI: ");
Serial.print(reading, BIN);
Serial.println();

delay(1000);
}
</syntaxhighlight>

← Older revision		Revision as of 14:24, 2 March 2018
Line 72:		Line 72:
	</syntaxhighlight>		</syntaxhighlight>

		+	===Sharing the MISO line with other SPI devices===
		+
		+	Connecting the serial output Q7 directly to the MISO line of the master is only allowable if no other devices on the bus share the MISO line. This is because a legitimate SPI device is expected to tri-state its MISO line when the device is not selected in order to avoid bus contention.
		+
		+	* Even though obviously it's the principle of the thing, for production purposes you might consider substituting a different device that already does what you need.
		+	** The 74HC589 is similar to (but not pin-compatible with) the '165, but with a tri-state MISO line. It would replace a '165 and probably be capable of chaining with other '165 devices. It costs only a tiny bit more than a '165 and substantially less than a single '165 plus a separate buffer. Some will find issue with the fact that there apparently only one supplier (ON Semiconductor).
		+	** Full I/O expanders such as the MCP23S08 (8-bit) and MCP23S17 (16-bit) exist that use the SPI bus at full speed. Such an I/O expander is substantially more expensive than the equivalent shift registers (at current prices an MCP23S17 is 2:1 the combined '165 and '595 it would approximately replace) and a bit more complicated to use, but in exchange provide luxury I/O ports with the works, including direction control, configurable input pullups, and per-port interrupt on change.
		+	*** Such I/O expanders are also available for I2C bus instead (see also MCP23008, MCP23017).
		+	* A tri-state buffer can be placed between Q7 and MISO that is switched by the /SS line.
		+	** The 74HC125 contains four buffers, each with its own /OE pin. This could be used to make multiple '165-like devices electrically compatible with SPI.
		+	** The 74HC1G125 is a single-gate version of the 74HC125, suitable for a single '165-like device. However, currently, it costs a little more than the ordinary '125.
		+	** The 74HC595 has its own serial output Q7 that is switched by its /OE pin. Chaining with a '595 in this way would require a dummy byte to be shifted through before the input could be read, and the '595 would probably not be usable for output by the application because its /OE would need to be set to disabled most of the time.
		+	** A 74HC589-based device (see above) at the head of the chain before any actual '165-like devices would take care of the issue.
		+	* If you control all devices on the bus, you may be able to convert MISO on all devices on the line to open-drain by adding (an inverter and) a MOSFET to the device output. In the case of a '165, the /Q7 output can be used instead of the Q7 to preserve the polarity.

	==74HC595 and similar==		==74HC595 and similar==

@@ Line 118: / Line 118: @@
    delay(100);
+}
 </syntaxhighlight>

← Older revision		Revision as of 21:38, 24 February 2018
Line 74:		Line 74:

	==74HC595 and similar==		==74HC595 and similar==
−
−	~~Note: The following was tested on a shift register module with soldering defects on some outputs, so this code is only ''probably'' right. Recheck on known working hardware.~~

	<syntaxhighlight lang=cpp>		<syntaxhighlight lang=cpp>

@@ Line 125: / Line 125: @@
 <syntaxhighlight lang=cpp>
-...
+#include <SPI.h>
 </syntaxhighlight>

@@ Line 69: / Line 69: @@
    delay(1000);
+}
 </syntaxhighlight>

@@ Line 14: / Line 14: @@
 //  13    SCK   shift clock (SH_CP, CP, DIP #2)
-// Note that the storage clock and the NSS can be anywhere. Rumor says that
+// Note that the storage clock and the NSS can be anywhere. The UNO pin 10
-// on the UNO pin 10 must be OUTPUT for the SPI master to work, but it need
+// must be OUTPUT for the SPI master to work (the "NSS" functionality of the
-// not be the actual select pin.
+// pin is applicable for SPI *in slave mode* when it is an input), but it
 const uint8_t IM_STO = 9;